Inverter



R. J. EHRET Jan. 22, 1963 INVERTER 2 Sheets-Sheet 1 Filed Aug. 5, 1959 ROBERT J. EHRET INVENTOR.

ATTORNEYS Jan. 22, 1963 R. J, EHRET 3,075,135.

INVERTER Filed Aug. 5, 1959 2 Sheets-Sheet 2 (3 /////////A I/l/I/l/l/J 'Q E'm%mmmm FIG. 2

ROBERT J. EHRET INVENTOR.

ATTORNEYS United States Patent Ofi' 3,ti?5,l35 Patented Jan. 22, 1963 3,075,135 TNVER E Robert J. Ehret, Los Altos, alii., assignor to Arnpex Corporation, Redwood City, Caiifi, a corporation of California Filed Aug. 5, 1959, fier. No. 831,851 4 'Clairns. (Cl. 321-18) This invention relates generally to an inverter and more particularly to a transistorized inverter.

In transistorized inverters it is desirable to operate the transistors as switches whereby they are either turned fully on or fully oil. When transistors are operated as switches, the power which they must dissipate is relatively small, for when the transistor is on, the voltage is relatively low, and when the transistor is off the current is relatively low. However, inverters of this type generally provide a squarewave output which is rich in harmonic content. If the output is employed to drive synchronous motors or other machinery, the harmonics do not contribute to useful work but are converted to heat. A further disadvantage with inverters of the prior art is that, in order to obtain regulated output power, the power supply for the inverters must be regulated.

It is a general object of the present invention to provide an improved transistorized inverter.

It is another object of the present invention to provide a transistorized inverter in which the transistors are employed as switches and in which the output wave has a low harmonic content.

'It is a further object of the present invention to provide a transistorized inverter which operates from an unregulated D.-C. power and provides regulated out put power.

It is still a further object of the present invention to provide a transistorized inverter which employs a saturable core reactor to regulate the output power.

These and other objects of the invention will become more clearly apparent from the following description when taken in conjunction with the accompanying drawmg.

Referring to the drawing:

FIGURE 1 is a circuit diagram of an inverter in accordance with the present invention; and

FIGURE 2 shows the waveforms at various points in the circuit of FIGURE 1.

Referring to FIGURE 1, the unregulated D.-C. voltage is applied to the lines ill and 12 as indicated by the voltage notation +V and V. Alternating current power is available at the output winding 13 of the transformer 14. The output winding 13 includes output terminals 16 and 17 and the center tap terminal 13.

Synchronizing signals control the frequency of the output wave. These signals are applied at the terminal 19 and operated upon to form triggering pulses for application to the switching transistors 21 and 22. The transistors 21 and 22 are connected in circuit with a primary winding 23 of the output transformer 14.

The switching transistor-s21 and 22 have their emitter terminals connected to the line 11 through current limiting resistors 26 and 2.7, respectively. The collectors of the transistors 2-1 and 22 are connected to the terminals 28 and 29 of the primary 23, respectively. A network including the capacitor 31 and resistor 32 is connected between the collectors of the switching transistors 21 and 22. Triggering pulses are applied to the bases of the transistors 21 and 22 in series with the windings 33 and 34, respectively. The windings 33 and 34 are coupled to the core of the transformer and serve to provide a voltage between the base and emitter of the transistors as will be presently described.

The center tap 3d of the winding 23 is connected to the emitter of a common switching transistor 37 through resistor 38. The collector of the transistor 37 is connected directly to the line 12. The line 12 is connected to the common terminal of the resistors 39 and :4 connected in parallel with the resistors ill and 42. The base of the transistor 37 is connected to receive switching pulses either from the amplifier including transistor 43 or from the rectifiers 44 and 46.

The rectifiers 44 and 4d are connected as a fullwave rectifier to the secondary winding 4% of a saturable core reactor 49. The primary winding 51 of the saturable core reactor is coupled to the core of the output transformer by the winding 52. A potentiometer 53 serves to provide a predetermined fraction of the voltage induced on winding 52 to the primary winding 51 of the saturable core reactor.

The circuit described thus far serves as the inverter and regulator of the present invention. The remainder of the circuit shown in FlGURE l is adapted to receive synchronizing pulses at the terminal 19 and to provide suitable triggering pulses for the transistor switches 21 and 22, as previously described. it will be apparent after the description of the operation of the inverter and regulator that means other than those shown may be employed for supplying triggering pulses to the tran sistors 2i and 22.

Operation of the inverter and regulator is as follows: In the absence of signal from the transformer 14, the switching transistors 21 and 22 are normally biased on by the voltage applied from the resistive divider including resistors 41 and 42. The common transistor 37 is normally biased off by the voltage applied from resistors M7 and i127.

Assume that pulses of the type shown in FIGURE 2A are applied to the base of the switching transistor 21 along the line 55 and that pulses of the type shown in FIGURE 23 are applied along the line 57 to the base of the switching transistor 2.2. Assume further that before the pulses are applied, transistors 21 and 22 are biased on and that the transistor 37 is biased off. When the positive pulse 5%, FIGURE 2A, is aplied along the line 56, it will start to turn off the transistor 2.1. As the transistor starts to turn off, a voltage is induced in the windings associated with the core of the transformer. The voltage induced in the winding 34 is such that the transistor 22 is biased on more strongly. A voltage is also induced in the winding 52 which is applied through the saturable core reactor 49 and rectifier 44 to the base of the common transistor 37 tending to turn the transistor 37 on. Thus, a circuit is completed from the line ll through resistor 27, through emitter to collector path of the transistor 22, through the portion of the primary winding including terminal 2?, from the center tap 36 of winding 23, through the resistor 38, through the emitter to collector path of the transistor 3'7 and to the common line 12. A voltage will appear across the various windings, which voltage tends to more strongly turn off the transistor-21, and more strongly turn on the transistors 22 and 37. The switching action takes place almost instantaneously because of the coupling arrangement described.

Referring to FIGURE 2, the shaded areas associated with FIGURE 20 represent the on condition for the transistor 21; the shaded areas in FIGURE 21) represent the on condition for the transistor 22; and the shaded areas, FIGURE 2E, represent the on condition for the transistor 37. The condition just described corresponds to the shaded areas 59 and 6t The saturable core reactor will saturate after'predetermined volt-seconds have been applied. When the reactor saturates, there is no longer any change in flux. The induced voltage in the winding 43 drops to zero, and thus the voltage applied to the rectifiers 44 and as will drop to zero and the transistor 37 will he biased oil. The induced voltage in winding 33 is reduced to zero and th transistor 21 is biased on. Thus, the transistors 21 and 22 are on, and the transistor 37 is off. There is provided a closed path through the collector-emitter junction of the transistors 21 and 22 connecting the terminals 23 and 29 as the primary of the winding 23. Flux in the transformer M tends to maintain itself and spikes in the output winding due to collapse of fields minimized. The output voltage is the type shown at 63 in which t e area under the curve has a constant value.

The next switching pulse '66 switches ofi the transistor 22. This gives rise to a similar chain of eilects,

iore strongly turning on the transistors 21 and 37 and turning ott transistor 22. An output wave of the type shown at 63 results. Here again, when the core of saturable core reactor 49 saturates, the transistor 37 is switched off and the transistors 21 and 22 are both switched on to prevent the collapse of the flux in the field.

The output wave available at the terminals 16 and 17 has a frequency dependent upon the frequency of the pulses S8 and $6 and a waveshape which is dependent upon the setting of the potentiometer 53. By appropriately selecting the position of the potentiometer 53, an output waveform, FIGURE 2F, is created for which the Fourier analysis will show a minimum of third harmonics. Thus, filters and the like can be eliminated, if desired, without overheating of associated equipment due to third harmonic voltages.

Referring to FTGURE 1, the remainder of the circuit shows means for generating the triggering pulses S and 66 from a sync signal applied at 1%. The sync pulse applied at the terminal 19 is limited by the diode 71 and applied to the base of the transistor '72 which is connected in an amplifying circuit. The amplified output from the transistor 72 is applied to the phase splitter including the transistors "73 and '74 which provide output waves, having a 180 phase relationship, at the lines 76 and 77. These Waves are applied to the combination of capacitor 78 and resistor '79, and capacitor 81 and resistor '32, respectively, and then applied to the bases of the transistors 83 and 84 which are connected in an amplifying circuit. The signal is further amplified by the circuit including transistors 86 and 8-7 and then applied through the capacitors 88 and 89 to the base of the switching transistors 21 and 22.

In order to initially start the inverter, a triggering pulse is required for the transistor 37. Such a pulse may be obtained from the line 76 and coupled to the base of the amplifying transistor i i. The output of the transistor 91 is amplified by the transistor 43 and applied to the base of the switching transistor 37. Thus, the transistor 37 is switched by each of the pulses derived at the line 76 to thereby maintain the same in synchronism with the incoming synchronizing pulses.

An inverter in accordance with FIGURE 1 was constructed in which the various components had the following values.

Voltages:

+V "Volts-.. +24 -V do -24 Transistors 211. 2Nl74- 22 2N174 37 2N174 43 2N383 '7 2N167 73 2N167 74 2N167 33 2N383 8d 2N383 86 2N268 i Transistors z-Cont.

87 2N268 91 2Nl67 Diodes:

14' ltlNl 4d lONl 71 lNZOt) 92 10Nl Resistors:

26 "ohms" 0.1 27 do 0.1 32 do 22 33 do 0x1 39 do 50 do 50 at do 5 d2 do 5 53 do 25 7h do 22K 32 do 22K 93 do2 1K 94 do 1K 96 do 4 7K 98 do 22K 99 do 4.7K ltlll do 22K 1G2 do 3.3K Th3 do 1.5K 104 do 2 2i 1M do 220 107 do 4.7K 103 do 4.7K 1G9 do 4.7K 1H do 1 112 c do 1 113 d0 4.7K 114 do 680 116 do 680 117 do 118 do 220 3119 do 10 3121 do 2.5 11.22 do 2.5 123 do 75 124 do 75 126 do- 5 127 do 15 Capacitors:

31 mf 1 '78 m-f .l 81 mf .1 33 mf 15 89 mf 15 131 mt .47 132 mf .02 P 133 mf l5 Transformer turns:

33 IOT Transformer core-Magnetics 500262A.

Synchronizing pulses having a frequency of 62 c.p.s. were applied to the inverter.

The resistor 53 was adjusted and the harmonic content of the output wave was 1% 3RD. The input voltage Was varied between 15 v. and 30 v., and the output power varied only 4%. 1

Thus, it is seen that an inverter which is adapted to provide constant output power from an unregulated D.-C. supply is provided. The circuit is such that the harmonic content of the output wave is satisfactory for operating motors and the like. The transistors employed with the output circuit are operated as switches whereby they are required to have minimum power dissipation capabilities.

I claim:

1. An inverter including first and second input lines coupled to a source of direct current, a transformer having a core and at least a center tapped primary winding and a secondary winding, said secondary winding adapted to supply power to an associated alternating current load, a pair of switching transistors serving to selectively connect the first line to opposite terminals of the primary winding in response to switching signals, a common switching transistor connected between the center tap of said primary winding and said other line, a saturable core reactor, means for coupling the input of said saturable core reactor to the flux variations in the core of said transformer, said common switching transistor being connected to be switched by the output of said saturable core reactor.

2. An inverter including first and second input lines coupled to a source of direct current, a transformer having a core and at least primary and secondary windings, a pair of switching transistors coupled between the primary winding and said first line, a source of synchronizing pulses coupled to the pair of transistors for alternately conditioning the transistors for conduction, a common switching transistor coupled between a center tap of the primary winding and the second line, and means coupled to the transformer core and to the common switching transistor for selectively completing a current path between the first and second lines through the primary winding, whereby an alternating output is induced in the secondary winding.

.3. An inverter comprising first and second lines coupled to a source of direct current, a transformer having a core and at least primary and secondary windings with the primary winding having first and second terminals and a center tap, first and second switching transistors respectively coupled between the first and second terminals and the first line, means for applying switching pulses to the first and second transistors, a third switching transistor coupled between the center tap and the second line, and means including a saturable core transformer coupled between the transformer core and the third switching transistor for controlling current flow between the first and second lines through the primary winding whereby an alternating output is induced in the secondary winding.

4. An inverter comprising first and second lines coupled to a source of direct current, a transformer having a core, a primary winding including first and second terminals and a center tap, first and second transistors each having base, emitter, and collector electrodes with the collector of the first transistor connected to the first terminal and the collector of the second transistor connected to the second terminal, means coupled to the base of each of the first and second transistors for applying separate switching signals at spaced intervals, a first secondary winding of the transformer coupled between base and emitter of the first transistor for providing bias, a secondary winding of the transformer coupled between base and emitter of the second transistor for providing bias, the first line being coupled to the emitter of both the first and second transistors, a third transistor having base, emitter, and collector electrodes with the emittercollector current path connected between the center tap and the second line, a third secondary winding of the transformer coupled to drive a saturable reactor with the output of the reactor coupled between the base and emitter electrodes of the third transistor to switch the transistor between conduction and nonconduction, and an output winding of the transformer having terminals providing an alternating current output controlled by Witching pulses and the saturable reactor.

References Qited in the file of this patent UNITED STATES PATENTS 2,959,745 Grieg Nov. 8, 1960 2,968,738 Pintell Jan. 17, 1961 2,968,739 Mohler Jan. 17, 1961 OTHER REFERENCES 

4. AN INVERTER COMPRISING FIRST AND SECOND LINES COUPLED TO A SOURCE OF DIRECT CURRENT, A TRANSFORMER HAVING A CORE, A PRIMARY WINDING INCLUDING FIRST AND SECOND TERMINALS AND A CENTER TAP, FIRST AND SECOND TRANSISTORS EACH HAVING BASE, EMITTER, AND COLLECTOR ELECTRODES WITH THE COLLECTOR OF THE FIRST TRANSISTOR CONNECTED TO THE FIRST TERMINAL AND THE COLLECTOR OF THE SECOND TRANSISTOR CONNECTED TO THE SECOND TERMINAL, MEANS COUPLED TO THE BASE OF EACH OF THE FIRST AND SECOND TRANSISTORS FOR APPLYING SEPARATE SWITCHING SIGNALS AT SPACED INTERVALS, A FIRST SECONDARY WINDING OF THE TRANSFORMER COUPLED BETWEEN BASE AND EMITTER OF THE FIRST TRANSISTOR FOR PROVIDING BIAS, A SECONDARY WINDING OF THE TRANSFORMER COUPLED BETWEEN BASE AND EMITTER OF THE SECOND TRANSISTOR FOR PROVIDING BIAS, THE FIRST LINE BEING COUPLED TO THE EMITTER OF BOTH THE FIRST AND SECOND TRANSISTORS, A THIRD TRANSISTOR HAVING BASE, EMITTER, AND COLLECTOR ELECTRODES WITH THE EMITTERCOLLECTOR CURRENT PATH CONNECTED BETWEEN THE CENTER TAP AND THE SECOND LINE, A THIRD SECONDARY WINDING OF THE TRANSFORMER COUPLED TO DRIVE A SATURABLE REACTOR WITH THE OUTPUT OF THE REACTOR COUPLED BETWEEN THE BASE AND EMITTER ELECTRODES OF THE THIRD TRANSISTOR TO SWITCH THE TRANSISTOR BETWEEN CONDUCTION AND NONCONDUCTION, AND AN OUTPUT WINDING OF THE TRANSFORMER HAVING TERMINALS PROVIDING AN ALTERNATING CURRENT OUTPUT CONTROLLED BY SWITCHING PULSES AND THE SATURABLE REACTOR. 